`include "defines.v"

module wb(

    input                       rd_w_ena_i,
    input       [`REG_BUS]      rd_w_addr_i,
    input       [`REG_WIDTH]    rd_w_data_i,
    input                       wb_halt_ena_i,
    input                       wb_skip_i,

    output wire                 rd_w_ena_o,
    output wire [`REG_BUS]      rd_w_addr_o,
    output wire [`REG_WIDTH]    rd_w_data_o,
    output wire                 wb_halt_ena_o,
    output wire                 wb_skip_o

);

    assign rd_w_ena_o    = rd_w_ena_i;
    assign rd_w_addr_o   = rd_w_addr_i;
    assign rd_w_data_o   = rd_w_data_i;
    assign wb_halt_ena_o = wb_halt_ena_i;
    assign wb_skip_o     = wb_skip_i;

endmodule